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129 morgan drive, norwood ma 02062 1 voice: (781) 551 - 9450 fax: (781) 440 - 9528 email: sales@apogeeddx.com copyright apogee technology, inc 2000 november 2001 (all rights reserved) doc #1000002 - 09 all - digital high efficiency power amplifier general description the ddx - 2000 controller and ddx - 2060 power device is an all - digital stereo amplifier chip set that can provide up to 35 watts per channel of audio power at very high efficiency. the ddx - 2 000 controller includes two channels of ddx processing, digital volume control, mute and special processing to reduce distortion associated with signal clipping. the controller accepts standard pcm serial formats and operates from an external 256*fs cloc k or from a crystal. the ddx - 2060 power device is a dual channel class - d h - bridge power device that has a logic interface, integrated bridge driver, high efficiency mosfet output transistors and protection circuitry. the benefits of this system are the a ll - digital design that eliminates the need for a digital to analog converter (dac) and the high efficiency operation derived from the use of apogee's patented damped ternary pulse width modulation (pwm). this approach provides an efficiency advantage over conventional class - d designs and up to three times the efficiency of typical class a/b amplifiers with music input signals. features high output capability 2x35w into 8 w @ <1% thd+ n 1x70w into 4 w @ <1% thd+n single supply (+9v to +30v) high efficiency, >88% digital volume control, anti - clipping and automatic mute thermal overload and short circuit protection benefits complete surface mount design small package - no heat sink p ower supply savings all digital - no dac applications digital powered speakers pc sound cards car audio surround sound systems digital audio components DDX-2000/2060 ddx - 2000 controller ddx - 2060 power device lp filter lp filter i 2 s digital audio left right 2 pwm1 v+ 3 2 pwm2 volume 3 mute reset clock power down +vl
____________ ddx - 2000/2060 2 details are subject to change without notice. absolute maximum ratings [1] ddx - 2000 symbol parameter value unit vl power supply voltage - 0.3v to +4.6v v note [2] logic inp uts - 0.3v to +6.0v v tstg storage temperature range - 40 to +150 c ddx - 2060 symbol parameter value unit vcc power supply voltage 40v v vl input logic reference 5.5v v tj operating junction temperature range - 40 to +150 c tstg storage temperature ra nge - 40 to +150 c recommended operating conditions [3] ddx - 2000 symbol parameter min typ max unit vl power supply voltage 3.3 v vih note 2 logic inputs, high 2.0 5.5 v vil logic inputs, low 0.8 v fs pcm input sample rate 32 48 khz t a ambient temperature 0 70 c ddx - 2060 symbol parameter min typ max unit vcc power supply voltage 10.0 28.0 v vl input logic reference 3.3 v vih logic inputs, high 1.7 v vil logic inputs, low 0.8 v iol output sink current, open - drain faul t and twarn 1 ma t a ambient temperature 0 70 c thermal data ddx - 2000 symbol parameter min typ max unit q ja thermal resistance junction - ambient 110 c/w ddx - 2060 symbol parameter min typ max uni t q jc thermal resistance junction - case (thermal pad) 2.5 c/w t j thermal shut - down junction temperature 150 c t h thermal shut - down hysteresis 25 c 1. permanent device damage may occur if absolute maximum ratings are exc eeded. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. sclk, sdata, lrclk, vmode, vclk/up, vdata/dn, smode, nrst, ace, mute are 5v input tolerant. 3. performance not guaranteed beyond recommended op erating conditions.
____________ ddx - 2000/2060 3 details are subject to change without notice. electrical characteristics[1] refer to circuit fig. 5. vcc=28v, f=1khz, ta=25c, rl=8 w , and measurement bandwidth 22khz . symbol parameter condition min typ max unit po output power thd+n <1% 35 wrms overvoltage protection threshold 30 35 v undervoltage protection threshold 7 9 v i l vl supply current for ddx - 2000 vl= +3.3v 90 1 00 ma i pd vcc supply current in powerdown 1 3 ma i q vcc quiescent current (hi - z state) hi - z state 26 ma i cc vcc supply current 2 - chan. switching at 384khz. 68 ma i sc short circuit current limit 3.0 5.0 6.5 a thd+n total harmonic distortion+noi se po=1.0 wrms po= 30 wrms .08 .33 .18 .50 % snr signal - to - noise ratio a - weighted 93 db h efficiency po=2 x 20w 87 % psrr power supply rejection ratio vrip= 1 vrms, 120hz, - 60 db input 60 db 1. characteristics are for the ddx - 2060 power device driven by ddx - 2000 processor.
____________ ddx - 2000/2060 4 details are subject to change without notice. d dx - 2000 pin function description audio serial interface (i 2 s) pin name pin no. description sclk [1] 1 input serial clock sdata [1] 2 input serial data lrclk [1, 2] 3 input left/right smode [1, 2] 20 serial mode select (0=left justified, 1= i 2 s. see f igure 3) gain/volume interface pin name pin no. description vmode [1, 2] 39 volume mode select vclk/up [1, 2] 40 volume data clock or increment up vdata/dn [1, 2] 41 volume serial data in or increment down ace [1, 2] 5 anti - clipping enable, active hi system clocking pin name pin no. description xi 11 256*fs oscillator/external 256*fs clock input xo 10 256*fs oscillator inlp 16 pll filter outlp 17 pll filter ddx output signals/control pin name pin no. description mute [1, 3] 38 active hi, se ts outputs to damped state outla 33 left channel output a outlb 32 left channel output b outra 26 right channel output a outrb 25 right channel output b power supplies/miscellaneous pin name pin no. description vl 4, 13, 15, 27, 29, 44 power gnd 9, 12, 14, 18, 19, 28, 34, 35, 37, 42, 43 ground nrst [1, 2, 4] 6, 7 system reset, active low. both pins must be connected for proper operation. nc 8, 21, 22, 23, 24, 30, 31, 36 no connect. must be left open. 1. denotes 5v input tolerance. 2. denotes 50k internal pullup. 3. denotes 50k internal pulldown. 4. denotes ttl schmitt input buffer. vt+ = 2.0v max. vt - = 0.7v min. typical hysteresis is 0.5v.
____________ ddx - 2000/2060 5 details are subject to change without notice. ddx 2060 pin function description pwm inputs pin no. description 29 left a logic input signal inlb left b logic input signal inra right a logic input signal inrb right b logic input signal control/miscellaneous pin name description pwrdn power down (0=shutdown, 1= normal). tri - 26 tri - ts hi - fault [1] 27 twarn [1] 28 (0=warning ic >= 130c, 1=normal). config [3] configuration (0=normal, 1=parallel operation for mono). nc do not connect. power o pin name pin no. outpl 16, 17 outnl 10, 11 outpr 8, 9 outnr 2, 3 pin name pin no. vcc[1p, 1n, 2p, 2n] 4, 7, 12, 15 pgnd[1p, 1n, 2p, 2n] 5, 6, 13, 14 vreg1 21, 22 vreg2 33, 34 vsig 35, 36 positive supply. 23 logic reference voltage. 19 logic reference ground. 1 substrate ground. 20 internal regulator ground. 1. - drain. 2. ase with the input. connect config pin 24 to vreg1 pins 21,22 to implement parallel operation for mono.
____________ ddx - 2000/2060 6 details are subject to change without notice. fig. 5a - typical application circuit (signal processing section)
- 2000/2060 7 fig. 5b - typical application circuit (power section)
____________ ddx - 2000/2060 8 details are subject to change without notice. typical pe rformance characteristics at vcc = 28v, 8 ohm load. fig 6: efficiency vs output power fig 7: frequency response fig 8: thd+n vs frequency fig 9: thd+n vs outpwr at 1 khz (w/ anticlipping disabled) -1 +1 -0.5 -0 +0.5 d b r c h 2 -1 +1 -0.5 -0 +0.5 d b r c h 1 20 20k 50 100 200 500 1k 2k 5k 10k hz 0 20 40 60 80 100 0 5 10 15 20 25 30 output power w efficiency % 0.01 20 0.02 0.05 0.1 0.2 0.5 1 2 5 10 t h d + n % 10m 50 20m 50m 100m 500m 1 2 5 10 20 w rms 0.006 1 0.01 0.02 0.05 0.1 0.2 0.5 t h d + n % 20 20k 50 100 200 500 1k 2k 5k 10k hz 1w 10w
____________ ddx - 2000/2060 9 details are subject to change without notice. typical performance charac teristics at vcc = 24v, 4 ohm load. fig 10: thd+n vs frequency typical performance characteristics at vcc = 28v, 4 ohm load, configured for mono. fig 12: thd+n vs frequency fig 11: thd+n vs outpwr at 1 khz (w/ anticlippi ng disabled) fig 13: thd+n vs outpwr at 1 khz (w/ anticlipping disabled) 0.006 1 0.01 0.02 0.05 0.1 0.2 0.5 t h d + n % 20 20k 50 100 200 500 1k 2k 5k 10k hz 1w 10w 0.006 1 0.01 0.02 0.05 0.1 0.2 0.5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz 2w 20w 0.01 20 0.02 0.05 0.1 0.2 0.5 1 2 5 10 t h d + n % 100m 100 200m 500m 1 2 5 10 20 50 w rms 0.01 20 0.02 0.05 0.1 0.2 0.5 1 2 5 10 t h d + n % 10m 60 20m 50m 100m 500m 1 2 5 10 20 w rms
____________ ddx - 2000/2060 10 details are subject to change without notice. system overview the ddx - 2000/2060 is an all - digital 2 - channel amplifier chip set that delivers up to 35 watts per channel at very high efficiency. the syst em consists of a ddx - 2000 controller, ddx - 2060 power device and an output filter. the ddx - 2000 controller accepts standard digital audio data and converts it to pwm logic level signals. the device also includes digital volume, muting and anti - clipping fu nctions. the ddx - 2060 is a dual channel h - bridge that converts ddx - 2000 pwm timing signals to power at the load. a passive low pass filter prior to the load attenuates the modulation carrier. the ddx - 2060 is protected against over - voltage, thermal and s hort circuit conditions. ddx - 2000 controller the ddx - 2000 controller is a 3.3v digital integrated circuit that converts serial pcm digital audio signals into apogee's patented damped ternary outputs. the device supports two modes of digital volume contr ol, mute and anti - clipping functions. a block diagram of the device is shown in figure 1. figure 1 - ddx - 2000 functional diagram audio serial interface the ddx - 2000 audio serial input was designed to interface with standard digital audio component s such as s/pdif receivers, surround sound decoders and digital signal processors. serial data input is controlled by three input pins: serial clock (sclk), serial data (sdata), and left/right clock (lrclk) in either i 2 s or left justified formats as contr olled by the serial mode pin (smode). the serial data formats and timing diagram are shown in figure 3. the ddx - 2000 utilizes serial data words of 16 bits and accepts data words up to 24 bits. volume interface the volume level of the ddx2000 pwm outputs can be adjusted by setting the left and right volume registers (voll and volr). these registers are seven bits with a step size of approximately - 0.75 db providing an adjustment range of ? 82.5 db to +12.0 db. table 1 shows the volume level as a functio n of the register values. following power - on - reset both volume registers are set to 0x26 or - 15.75 db. the volume registers, voll and volr, can be set with a serial data load using a micro - controller or similar device (serial mode) or by incrementing the volume register using control pins (toggle mode). this functionality is controlled using the volume mode select pin (vmode) and two multifunction pins; volume clock/volume up (vclk/up) and the volume data/volume down (vdata/dn). table 1 ? volume control volume register (voll, volr) hexadecimal volume (db) 0x00, 0x80 +12.0 0x01, 0x81 +11.25 0x02, 0x82 +10.5 . . . . . . 0x10, 0x90 0.0 0x11, 0x91 - 0.75 0x12, 0x92 - 1.5 . . . . . . 0x7e, 0xfe - 82.5 0x7f, 0xff mute when the vmode is logic - high ( internally pulled - up) the device operates in toggle mode. the volume registers (both voll and volr) can be incremented either up or down by bringing the inputs vclk/up or vdata/dn low. the volume register will increment at approximately 5 steps per secon d, for the first 1.4 seconds and then increase to approximately 10 steps per second until the upper or lower volume limits are reached or the input is released. a serial mode volume change is initiated by bringing vmode pin low. serial data is input on serial interface volume/ gain pwm generation anti- clipping system clocking sclk sdata lrclk vmode vclk/up vdata/dn ace outl[1:2] outr[1:2] xi xo lpin lpout mute
____________ ddx - 2000/2060 11 details are subject to change without notice. vdata/dn and is latched on the rising edge of the vclk/up input as shown in figure 4. after all eight bits are received vmode must be brought high to latch the volume register. note, each channel volume register must be written independently, (see table 1). for applications that provide digital volume control prior to the ddx - 2000, the attenuation register can be set to 0 db by pulling both the vclk/up and vdata/dn to ground, leaving vmode high. the ddx - 2000 includes an anti - clipping function to impro ve audio quality when using the internal volume control set to greater than 0 db. this function dynamically adjusts the volume level to significantly reduce distortion associated with signal clipping. this function is enabled by setting the anti - clipping enable (ace) pin high. when enabled, the maximum distortion will be limited regardless of the volume. for applications where maximum power is desired, the ace may be disabled and the output power and distortion will increase for volume settings which exce ed 0 db. system clocking the ddx - 2000 operates from a master clock source whose frequency is 256 times the input lrclk sample rate (256*fs). the device can accommodate sample rates from below 32 khz to above 48 khz. either external clock sources or the built in oscillator may be used. in designs that recover the clock (e.g., s/pdif), the 256*fs output can be utilized for the master system clock to provide synchronous operation. for systems that operate asynchronously, i.e., the crystal clock is no t exactly matched to the incoming serial data stream, the ddx - 2000 will automatically accommodate sample frequency mismatch up to 0.2 %. the accuracy of the master input clock will determine amplifier system performance. to meet the specified performanc e, random clock jitter must be less than 400ps p - p. ddx output control asserting the mute input (logic - high), the ddx - 2000 will command the zero state (load damping) which short - circuits the load to ground. the device also includes an automatic mute fu nction which is activated upon receipt of 2048 consecutive zero data words on both the left and right serial inputs. automatic transition from mute will occur on the first non - zero input word. ddx - 2060 power device the ddx - 2060 power device is a dual channel h - bridge that can deliver over 35 watts per channel of audio output power. the ddx - 2060 includes; a logic interface, integrated bridge drivers, high efficiency mosfet outputs and protection circuitry. two logic level signals per channel are use d to control high - speed mosfet switches to connect the speaker load to the input supply or to ground in a bridge configuration, according to apogee's patented damped ternary pwm. the ddx - 2060 includes over - current, thermal, and over - voltage protection and under - voltage lockout with automatic recovery. a thermal warning status is also provided. figure 2 - ddx - 2060 block diagram logic interface and decode the ddx - 2060 power outputs are controlled using two logic level timing signals. in order to provid e a proper logic interface, the vl input must operate from the ddx - 2000 logic supply. protection circuitry the ddx - 2060 includes protection circuitry for over - current, over - voltage, and thermal overload conditions. a thermal warning pin twarn is activa ted low (open - drain mosfet) when the ic temperature exceeds 130c, in advance of the thermal shutdown protection. when a fault condition is detected (logical or of over - current, over - voltage, and thermal), an internal fault logic i/f and decode left h - bridge protection circuitry inl[1:2] inr[1:2] pwrdn outpl fault vl tri - state outnl outpr outnr twarn regulators right h - bridge
____________ ddx - 2000/2060 12 details are subject to change without notice. signal acts to immediately disa ble the output power mosfets, placing both h - bridges in a high impedance state. at the same time an open - drain mosfet connected to the fault pin is switched on. there are two possible modes subsequent to activating a fault. the first is a shut - down mode . with fault (pull - up resistor) and tri - state pins independent, an activated fault will disable the device, signaling low at the fault output. the device may subsequently be reset to normal operation by toggling the tri - state pin from high - low - high using an external logic signal. the second is an automatic recovery mode. this is depicted in the application circuit, figure 5b. the fault and tri - state pins are shorted together and connected to a time constant circuit comprising r6 and c17. an activated fault will force a reset on the tri - state pin causing normal operation to resume following a delay determined by the time constant of the circuit. if the fault condition is still presented, the circuit operation will continue repeating until such time as the fault condition is removed. an increase in the time constant of the circuit will produce a lower recovery frequency tending toward safer operation. note, the automatic recovery mode may produce audible artifacts in a loudspeaker when a fault is activ ated. care must be taken in the overall system design so as not to exceed the protection thresholds under normal operation. power outputs the ddx - 2060 power and output pins are duplicated to provide a low impedance path for the devices bridged outputs. all duplicate power, ground and output pins must be connected for proper operation. the pwrdn or tri - state pins should be used to set all mosfets to the hi - z state during power - up until the logic power supply, vl, is well established. parallel output/hig h current operation the ddx - 2060 outputs can be connected in parallel for mono operation to increase the output current to a load. in this configuration the device can provide over 70w into 4 w. this mode is enabled with the config pin connected to vreg 1 and the inputs combined inla=inlb, inra=inrb and outputs combined outla=outlb, outra=outrb. additional information output filter a passive two - pole low pass filter is used on the ddx - 2060 power outputs to reconstruct the audio signal. system perfor mance can be significantly affected by the output filter design and choice of components. good audio performance can be obtained with low cost, solenoid type inductors having a dcr <.05 w and a 2a minimum rating. output filter capacitors should be the following types: common - mode capacitors should be 50v ceramic, x7r dialetric or 50v film types. differential capacitors should be 50v or greater film types. a filter design for 8 w load s is shown in the typical application circuit fig. 5b for reference. power dissipation/heat sink requirements the ddx - 2060 is a high efficiency dual channel design intended for audio applications up to 35 watts per channel. the power dissipation of th e device will depend primarily on the supply voltage, load impedance, and output modulation level. the ddx - 2060 surface mount package includes an exposed thermal pad on the bottom of the device to provide a direct thermal path from the integrated circuit to the pcb. this pad must be soldered to a low thermal impedance path at circuit ground potential for proper operation, e.g. a pcb ground plane. for continuous duty rated applications, careful consideration must be made to the overall thermal design. p erformance measurements class d amplifiers produce measurable switching distortion outside the audio bandwidth. apogee's ddx amplifier uses patented pwm modulation that significantly reduces the size of these products compared to typical class d designs. however, in order to obtain accurate performance measurements in the audio bandwidth (i.e., 20hz to 20khz) additional filtering is required. the typical performance data was taken using a brick wall filter with a break frequency of 20khz. this type of filter is often provided with audio measurement systems.
____________ ddx - 2000/2060 13 details are subject to change without notice. interface timing figure 3 - audio serial interface figure 4 - serial volume load timing vmode vclk vdata d6 d5 d4 d3 d2 ch a b notes: a) vdata hold time from vmode > 75 ns b) vclk hold time from vmode > 75 ns c) vdata setup to vclk > 50 ns d) vdata hold from vclk > 25 ns e) vdata setup to vmode > 75 ns f) vclk high time, clk lowtime > 100 ns g) ch = channel select. left=0, right=1. h) volume register (msb=d6, lsb=d0). c d d e d0 d1 lrclk left right sclk sdata lsb msb lsb msb msb lrclk l eft right sclk sdata lsb msb lsb msb msb smode=1 i 2 s smode=0 left justified
____________ ddx - 2000/2060 14 details are subject to change without notice. physical dimensions dimensions shown in mm ddx - 2060 - 36 pin power package dim. mm inch min. typ. max. min. typ. ma x. a 3 .60 0 .141 a1 0.10 0.30 0.004 0 . 012 a2 3.30 0 . 130 a3 0 0 .10 0 0 . 004 b 0 .22 0 .38 0 .008 0 . 015 c 0 .23 0 .32 0 .009 0 . 012 d (1) 15.80 16.00 0.622 0 . 630 d1 9.40 9.80 0.370 0 . 385 e 13.90 14.50 0.547 0 . 570 e 0 .65 0 .025 6 e3 11.05 0.435 e1 (1) 10.90 11.10 0.429 0 . 437 e2 2.90 0 . 114 e3 5.80 6.20 0.228 0 . 244 e4 2.90 3.20 0.114 0 . 126 g 0 0.10 0 0 .004 h 15.50 15.90 0.610 0 . 626 h 1 .10 0 .043 l 0 .80 1 .10 0 .031 0 . 043 n1 0 (max.) s8 (max.) ( 1 ): " d " a nd " e 1" do not i n c l ude m o l d f l as h or pro t rus i ons - m o l d f l as h or prot r u s i ons s hal l not ex c e ed 0. 15m m (0. 006 i n c h ) - cr i t i c al di m e ns i ons ar e " a3" , " e " and " g " . e a2 a e a1 detail a d 1 18 19 36 e1 e2 h x 45 detail a lead slug a3 s gage plane 0.35 l detail b detail b n n
____________ ddx - 2000/2060 15 details are subject to change without notice. physical dimensions dimensions shown in mm ddx - 2000 - 44 pin quad plastic flat package information furnished in this publication is believed to be accurate and reliable. however, apogee technology, inc. assumes no responsibility for its use, or for any infringements of patents or other rights of third parties that may result form its use. specifications in this publication are subject to change without notice. this publication supersedes and replaces all information previous supplied. apogee technology, inc. all rights reserved mirror finish

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